1. Field of the Invention
The present invention relates to sensing data in high speed, low power memory devices, and the like, and more particularly to preventing disturbance of sensing operations in memory devices due to noise.
2. Description of Related Art
In high speed memory devices, a clock signal used by a circuit reading data from the memory can have a period which is close to or shorter than a memory latency between a signal enabling access to a selected memory cell in the memory, and the time that a signal indicating data from the selected memory cell is available to be sensed. Also, output circuits which accept data from sense amplifiers on the memory can be responsive to the clock signal. High speed sense amplifiers are arranged so that signals from selected memory cells are sensed during sensing intervals at the times which correspond to a memory latency after applying the address signals to select the cells. If the clock signal transitions at the output circuits at a time which can cause noise at the sense amplifiers during the sensing intervals, errors can result in the data being read from the device. The timing of the noise generated is a function of the clock frequency, the memory latency and the clock latency. Thus, it is difficult to design a memory device that is immune to clock signal noise at the sense amplifiers over a specified range of operating frequencies. Also, as power supply voltages drop, the impact of noise is more severe.
FIGS. 1, 2 and 3 illustrate the operation of sense amplifiers and associated output circuits according to the prior art. As shown in FIG. 1, a first type of sense amplifier 10 is coupled to an array 11 by a data line 12. The data line 12 is connected to the input of inverter 13 and to the source of transistor 14. The output of the inverter 13 is connected to the gate of transistor 14. The drain of transistor 14 is connected through a load transistor M1 to a supply voltage VCC. The gate of the load transistor M1 is coupled to a start sensing signal Time1. A voltage Va is developed at the node 15 between the transistor 14 and the load transistor M1 when the start sensing signal Time1 is low in this embodiment. A latch circuit 16 has an input coupled to the node 15, and is responsive to a stop sensing signal Time2. The latch circuit captures the voltage Va developed at node 15 on the rising edge of the stop sensing signal Time2 in this embodiment. The output of the latch circuit 16 is coupled to an output circuit, comprising an input/output buffer 17 in this embodiment. The input/output buffer 17 is responsive to a clock signal CLK to accept the signal from the latch circuit 16 for supply to a device reading data from the memory.
FIG. 2 is a timing diagram illustrating the operation of the sense amplifier 10 of FIG. 1. The clock signal CLK is illustrated on trace 20. The start sensing signal Time1 is illustrated on trace 21. A stop sensing signal Time2 is illustrated on trace 22. The voltage Va developed on node 15 is illustrated on trace 23. In the timing diagram, the clock signal CLK has a period which is the sum of the width tWH between a rising edge and the next falling edge and the width tWL between a falling edge and the next rising edge. The start sensing signal Time1 goes low at time 25 and goes high at time 26. The stop sensing signal Time2 goes high at time 27. When the start sensing signal Time1 goes low, the voltage Va on note 15 is pre-charged to a high level 28. At time 26, the voltage Va on the node 15 is determined by the signal from the selected memory cell on the data line 12. If the signal from the selected memory cell is no current, then the voltage Va remains high during the sensing interval, and the data is interpreted as a logical “0” in this example. If the signal from the selected memory cell is current flow, then the voltage Va is pulled down during the sensing interval, and the data is interpreted as a logical “1” in this example. At time 27 when the stop sensing signal Time2 goes high, the latch circuit 16 captures the value of the voltage Va. The interval between time 26 and time 27 is the sensing interval. The sense amplifier is sensitive to noise occurring during the sensing interval that can affect operation of the latch circuit 16 or the level of the voltage Va. In this example, the clock 20 has a transition from high to low at time 29 during the sensing interval. This transition can generate noise at the node 15, and cause the latch circuit 16 to capture the wrong voltage, leading to erroneous data supplied to the I/O buffer 17.
FIG. 3 illustrates another sense amplifier implementation which encounters the same type of problem. In FIG. 3, a second type of sense amplifier 30 is coupled to an array 31 by a data line 32. A reference memory cell 33 (or array) is coupled to a reference line 34. Column select transistors 35 and 36 are adapted to connect data line 32 and reference line 34, respectively, to nodes 37 and 38. A first load transistor M1 is coupled between node 37 and a supply voltage VCC, and a second load transistor M2 is coupled between node 38 and the supply voltage VCC. The start sensing signal Time1 is coupled to the gates of the load transistors M1 and M2. Nodes 37 and 38 are connected as inputs to a comparator 39. The output of the comparator drives a voltage Va on node 40 which is connected to the input of a latch circuit 41. The latch circuit 41 is responsive to the stop sensing signal Time2. The output of the latch circuit 41 is coupled to an output circuit, such as I/O buffer 42 in this embodiment. The I/O buffer 42 is responsive to the clock signal CLK. The operation of the sense amplifier 30 has timing like that shown in FIG. 2. The voltage V1 and the voltage V2 are pre-charged when the start sense signal Time1 goes low, and are determined by a signal from the reference cell 33 and a signal from a selected memory cell in the array 31, respectively, when the start sense signal Time1 goes high. The comparator develops an output voltage Va on node 40 in response to the difference between voltage V1 and V2. The latch circuit 41 captures the voltage Va when the stop sensing signal Time2 goes high. The output of the latch circuit 41 is captured by the I/O buffer 42 in response to the clock signal CLK. Thus, if the clock signal has a transition during the sensing interval, then noise can affect the voltage Va on node 40, the voltages V1 and V2 on nodes 37 and 38, or operation of the circuitry, and lead to an error in the read operation.
It is desirable to provide a technique suitable for implementation in an integrated circuit memory device which prevents errors due to clock noise during sensing intervals.